CSP techniques are known. One technique is described in WO-A-93/24956, whose applicant is a co-assignee of the present invention, and which reference describes a method of manufacture of a component in which the face of the chip is completely covered with a layer of a resin coating and carries a series of metalizations connected to the contact pads of the chip, these pads beings embedded in the resin layer. The technique described in this document makes it possible to obtain a collective coating which is applied to the semiconductor wafer before the wafer is cut into chips, which technique minimizes the unit cost applied to each chip. However, in this technique, the resin coating covers the entirety of the wafer, which can generate two types of difficulties. First, the wafers produced today are increasing in size, the diameters of which have evolved from 4, 5, 6, 8 and up to 12 inches, and the total constraint generated on the wafer by the hardening of the resin, which is very hard once polymerized, can stress this wafer, and even cause cracks, breaks or cleavages. Second, the resin is in contact with the active part of the electronic circuits etched or formed on the various chips and can, in the long run, allow ionic contamination or various chemical pollutants permeate through the resin. Indeed, unlike the "chip carrier technologies", wherein the chip is completely insulated in a sealed case filled with a neutral gas such as nitrogen, the resin constitutes only an impediment, not a barrier, to the aggressions of the external medium, and consequently can reduce the long-term reliability of the electronic micropattern, which is not completely isolated.